Silicon Labs /Series1 /EFR32FG1V /EFR32FG1V131F32GM32 /PRS /CH3_CTRL

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Interpret as CH3_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIGSEL 0 (NONE)SOURCESEL0 (OFF)EDSEL 0 (STRETCH)STRETCH 0 (INV)INV 0 (ORPREV)ORPREV 0 (ANDNEXT)ANDNEXT 0 (ASYNC)ASYNC

EDSEL=OFF, SOURCESEL=NONE

Description

Channel Control Register

Fields

SIGSEL

Signal Select

SOURCESEL

Source Select

0 (NONE): No source selected

1 (PRSL): Peripheral Reflex System

2 (PRSH): Peripheral Reflex System

6 (ACMP0): Analog Comparator 0

7 (ACMP1): Analog Comparator 1

8 (ADC0): Analog to Digital Converter 0

16 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0

17 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1

28 (TIMER0): Timer 0

29 (TIMER1): Timer 1

41 (RTCC): Real-Time Counter and Calendar

48 (GPIOL): General purpose Input/Output

49 (GPIOH): General purpose Input/Output

52 (LETIMER0): Low Energy Timer 0

54 (PCNT0): Pulse Counter 0

60 (CRYOTIMER): CRYOTIMER

61 (CMU): Clock Management Unit

67 (CM4): undefined

EDSEL

Edge Detect Select

0 (OFF): Signal is left as it is

1 (POSEDGE): A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

2 (NEGEDGE): A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

3 (BOTHEDGES): A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

STRETCH

Stretch Channel Output

INV

Invert Channel

ORPREV

Or Previous

ANDNEXT

And Next

ASYNC

Asynchronous Reflex

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